When designing a via structure for a dielectric material, a via thus being an electrical connection structure for connection of conductors in different planes located adjacent to and in parallel to each other, as used in multilayer circuit boards or other multilayer substrates, several problems may be present. For thick substrates, the vias used for parallel transmission lines in a data bus cannot be placed with the same spacing as the transmission lines owing the aspect ratio of the via holes required in order to obtain a sufficient filling of the via holes with an electrically conductive material. A solution to this problem may be to make the substrate thinner where the vias are to be made.
Thus, in U.S. Pat. No. 5,322,816 a deep feed-through is disclosed using a via arranged at the bottom of a hole having inclining sidewalls. The hole is made by anisotropic etching of a Si-substrate and the walls thereof are covered with a metal material connecting through the via to a metal layer on the other side of the substrate. However, also this hole may have an upper diameter too large for being connected to densely located parallel transmission lines. A similar structure is disclosed in the published British patent application 2 150 749 A.
As disclosed in U.S. Pat. No. 4,613,891 an integrated circuit chip is with its active, upper side attached to the bottom side of a silicon wafer. A hole having sloping walls is etched in the wafer down to the chip. An electrically conducting path extends on the sloping walls and up and on to the top side of the wafer to connect conductive pads on the chip to other components. This structure is not suited for a via structure to be used in a multi-chip multi-level chip module comprising substrates and chips which are dismountable from each other.
Further, when the frequency of a signal, which is transmitted through a via increases, i.e. for high-frequency signals, there may be difficulties of having the signal transmitted without being too much distorted/attenuated or interfering with other signals. These difficulties are in turn associated with portions of the via which are not properly impedance matched.
In general, in order not to impose any too significant error to a transmitted high-frequency signal, the portion of a transmission line, which is not impedance matched, should not exceed 1/20 of the wavelength of the highest frequency of the signal transmitted through the dielectric medium. For example, for a frequency of 10 GHz and an effective relative dielectric constant equal to 3, 1/20 of the wavelength becomes equal to 1/2 mm, i.e. 500 .mu.m.
Thus, in the case where an electrical connection path from one component to another involves several vias, such as in a multilayer structure, where an electrical conducting path can pass through several substrates, i.e. through several planes containing electrical conductor paths, the total length of the not impedance matched portions of the connecting path can impose an error to a signal transmitted on this connecting path. In order that repeated not impedance matched portions of the connecting path will not influence the received signal noticeably, it is usually required:
that each not impedance matched portion of the connecting path has a length which is less than 1/20 of the wavelength of the signal, and PA1 that the not impedance matched portions are each separated by impedance matched portions each having a length larger than 1/2 of the wavelength of the signal, i.e. in the case described above by distances of at least 5 mm, which in particular for a connecting path containing repeated vias can not usually be guaranteed.
Another problem resides in that the dielectric medium supporting an electrically conductive path can act attenuating for signals having high frequencies.
A common solution to these problems is to use impedance matched vias designed as coaxial structures. Thus for instance U.S. Pat. No. 5,266,912 describes a multi-chip module, MCM, having external connections on coaxial pins.
A coaxial shielding is disclosed in U.S. Pat. No. 5,253,146 where an earthed intermediate electrically conducting shielding frame is fitted between two circuit boards. The frame has through-apertures enclosing coaxially electrical connectors connecting the circuit boards.
Another method of achieving impedance matching is disclosed in U.S. Pat. No. 5,338,970 describing a multilayered package using a shielding technique to improve high frequency performance of the package. This is obtained by using shield vias placed near conductive vias to create a two-wire transmission line having a controllable characteristic impedance.
However, it is for example very difficult to create coaxial via structures which are much longer or deeper than they are wide, i.e. have an aspect ratio much larger than 1. For instance, a typical distance between two parallel electrical conductors on the same side of a multi-chip module or MCM is 50-75 .mu.m, whereas the thickness of the substrate is between 1/2 and 1 mm. In order not to fan out the transmission lines at a via used for a signal bus comprising several parallel electrical conductor paths, coaxial structures having an outer diameter of approximately 20 .mu.m and a length of 0.5 mm would be required, i.e. structures having a ratio of their lengths to their thicknesses of 25:1, which can be a very difficult to achieve practically.
For example, assume that a coaxial structure having an outer dimension, i.e. the diameter of the outside of the shielding metal, of 25 .mu.m and a characteristic impedance of 50 ohms is required. Also assume that the thickness of the shielding metal is 3 .mu.m. This results in an outer diameter of the insulator of 19 .mu.m. Further assume that the relative dielectric constant of the insulator is equal to 3, which according to the equation EQU Z.sub.0 =59.97* sqrt(1/.di-elect cons..sub.r)*ln(R/r)
where .di-elect cons..sub.r is the relative dielectric constant of the insulator, R and r are outer and inner diameters of the insulator respectively, results in that the diameter of the inner conductor is 4.5 .mu.m for 50 Ohm. In order to cover the walls of the 25 .mu.m hole approximately uniformly with the shielding metal, some form of vapour phase or liquid phase deposition is required for a length or depth-to-diameter ratio of approximately 26 in this case, since evaporation or similar methods do not provide a satisfying uniformity of the layer produced. For metals having a high conductivity, a first deposition can be obtained from a non-electric plating, which can provide a very uniform but probably thinner layer.
This layer can by thickened by means of electrolytic plating, but it will be difficult to preserve a uniform thickness due to transport and current limitations. Fairly uniform layers can be obtained from tungsten W directly from a vapour phase. However, the metal W has a relatively high electrical resistivity and may be unsuitable as a shielding material.
However, it should be possible to deposit relatively uniformly, directly from a vapour phase, an insulator of the polymer material "Pyraline", and since, when depositing this material, the deposition will occur mono-layer by mono-layer, it should be possible to obtain uniform depositions also at length/diameter ratios of about 20, such as in this case.
The most difficult problem is associated with producing the inner, central conductor.
A diameter of 4.5 .mu.m results in a length/diameter ratio of 111 according to the discussion above, which in turn results in that probably every kind of deposition method used for producing such a very thin plug will be suffering from some form of transport limitation resulting in a large risk for the ends of the through-hole to be closed before a sufficiently thick metal layer has been deposited on the interior portions of the walls of the hole.